TetraMem’s 6-dimension co-design and co-optimization approach is a highly integrated methodology necessary for successfully implementing emerging analog in-memory computing (IMC) technologies, such as multi-level RRAM (computing memristors).

In traditional digital computing (based on the von Neumann architecture), design is highly modular. Engineers can work on different components—such as writing software or designing hardware—independently because solid-state transistors rely on well-understood physical laws and highly predictive models.

However, emerging IMC devices like RRAM involve complex interactions of materials, thermal chemistry, and electrical processes that are difficult to model. When an RRAM device is manufactured, its electrical operations (like programming and reading data) directly affect critical performance metrics such as error rates and endurance. Therefore, to make this technology work reliably, engineers cannot isolate the hardware from the software.

The six dimensions that must be co-designed simultaneously are:

1. Materials
2. Process (Fabrication)
3. Device (Physics)
4. Circuit
5. Algorithm
6. Application

By integrating expertise across all of these levels, the system can compensate for physical hardware limitations using software and circuit design. For example, as an analog crossbar array scales up in size, physical non-idealities like wire resistance, device defects, and thermal noise can severely degrade computing accuracy. Using this 6-dimensional approach, engineers can develop sophisticated mapping algorithms at the Algorithm level to compensate for the physical parasitic effects occurring at the Device and Circuit levels.

Ultimately, tightly coupling these six dimensions allows for the creation of manufacturable, large-scale multi-level memristor arrays that deliver highly accurate and energy-efficient AI computation for real-world applications.

Read more about our technology here.